In physical interfaces for memory applications, e.g. for so-called DDR memories, various kinds of signals are used to transmit data from or to the memory and to control the memory. These are especially control clock signals, data signals and sampling signals, so-called strobe signals, and also command and addressing signals. For effective communication between the memory and the interface it is necessary to set the phase relationships of these signals mutually or relative to an external clock signal.
To set the desired phase relationships between the signals it is common to use so-called delay locked loops. These are delay-locked loops which compare a clock signal with a delayed clock signal and automatically control the delay in such a way that the phase relationship of the clock signal and the delayed clock signal adopts a fixed value. A delay-locked loop can especially also delay in a controlled manner clock-type signals which do not have full periodicity, i.e. are only periodic in sections.
Examples of delay-locked loops of this kind are illustrated in FIGS. 8(a) and (b). The delay-locked loop of FIG. 8(a) receives a clock signal 1 as input signal. The clock signal is delayed by a delaying means 82 by a specific amount of time which can be set by a control signal 88. The output signal of the delaying means 82 thus forms a delayed clock signal. The delayed clock signal is compared by comparison means 84 with the non-delayed clock signal 1 in respect of the relative phase position. An output signal of the comparison means 84, generated on the basis of the comparison of the clock signal 1 with the delayed clock signal, is fed to the delaying means 82 as the control signal 88 via a loop filter 86.
An alternative form of delay-locked loop is illustrated in FIG. 8(b). This corresponds in respect of the delaying means 82, the comparison means 84 and the loop filter 86 to the delay-locked loop already described above using FIG. 8(a). However, the difference in this case is that two clock signals 1, 1a are fed to the delay-locked loop and their phase relationship is set by the delay-locked loop. This is achieved in that clock signal 1 is delayed by the delaying means 82 in order to generate the delayed clock signal, while the delayed clock signal is compared by the comparison means 84 with clock signal 1a, which thus has the function of a reference clock signal. The difference between the delay-locked loops of FIGS. 8(a) and (b) is consequently that in one case the phase relationship is set in respect of the non-delayed clock signal 1, while in the other case the phase relationship is set in respect of the reference clock signal 1a. The reference clock signal 1a can, for example, be derived externally from clock signal 1.
It is normally necessary with memory interfaces not only that a specific phase relationship is set, but that the phase position can also be set individually in each case for the different signals. In this connection it is known to configure a device for generating clock signals with controlled delay on the so-called master-slave principle. It is usual in such cases to use a delay chain with several delay stages or elements as delaying means. In a master delay loop the delay of the delaying means is firstly adjusted in such a way that there is a fixed phase relationship between the output signal of the delaying means and the non-delayed clock signal or the reference clock signal. The actual generation of the delayed clock signals is done by slave delay loops which are constructed identically to the master delay loop, but do not have their own control loop. The control signal of the master delay loop is then used as control signal for the delaying means of the slave delay loop. A delayed output clock signal is generated in that signals are tapped from the individual delay steps of the delaying means via a multiplexer. The delayed clock signals tapped in this way normally correspond to a fixed fraction of the delay set by the master delay loop. In this way it is possible with the slave delay loops to select the desired phase relationship between the clock signal or reference clock signal and the respective delayed signal individually. It is further possible to locate the generation of delayed clock signals flexibly, for example near the place where the delayed clock signal is being used.
FIG. 9 shows schematically a circuit block, configured on the master-slave principle, for generating and synchronising data and sampling signals in a memory interface for a memory device. The circuit block comprises a master delay-locked loop 100′, to which a clock signal to be delayed is fed as input signal. The master delay-locked loop 100′ delays the clock signal 1 by a specific amount of time, a defined phase relationship being set between the clock signal 1 and the delayed clock signal. To set the defined phase relationship the master delay-locked loop 100′ internally generates a control signal via which delaying means 110′ of the master delay-locked loop 100′ are controlled. The control signal of the master delay-locked loop 100′ is available at a signal output of the master delay-locked loop 100′ and is used to control a slave delay-locked loop 300.
The delaying means 110′ of the master delay-locked loop 100′ and of slave delay-locked loop 300′ are formed by identical delay chains with several delay elements 115′. The control signal which is generated by the master delay-locked loop 100′ controls in particular the delay supplied by one of the delay elements 115′ of the delaying means 110′. By tapping at the outputs of the individual delay elements 115′ of the delaying means 110′ both of the master delay-locked loop 100′ and of the slave delay-locked loop 300′, delayed clock signals can be tapped, which after adjustment of the master delay-locked loop 100′ have different delays, which correspond in each case to a defined fraction of the period length of the clock signal 1. The output signals of the individual delay elements 115′ are fed to multiplexers 120′, 320′, which generate output clock signals 3a, 3b, 3c by selecting the different delayed clock signals.
The phase relationship of the output clock signals 3a, 3b, 3c to the non-delayed clock signal is set by appropriate driving of the multiplexers 120′, 320′. For this values for the desired phase relationship are selected from lists stored in a memory 150′, 350′ and transmitted to a control register 130′, 330′. These values feed an appropriate control signal to the multiplexer 120′, 320′.
Output clock signal 3a acts as input signal for a sampling signal generating block 50′ which generates a sampling signal 3′ on the basis of output clock signal 3a. Output clock signal 3b is fed to a synchronisation block 60′ which synchronises write data signals 6, to be written into the memory, with output clock signal 3b, in order in this way to generate a memory data signal 4 synchronised with output clock signal 3b for write processes.
The master delay-locked loop 100′ generates output clock signals 3a, 3b, on the basis of the non-delayed clock signal 1. The slave delay-locked loop 300′, on the other hand, uses the sampling signal 3′ as input signal. A delay of the not fully periodic sampling signal 3′ is possible owing to the use of delay-locked loops. A desired phase relationship between the sampling signal 3′ and output clock signal 3c is set for read processes by slave delay-locked loop 300′. Output clock signal 3c is fed to a synchronisation block 70′ which generates a read data signal 5 synchronised with the clock signal 1 on the basis of a data signal 4 received from the memory. For this the clock signal 1 is additionally fed to the synchronisation block 70′.
For bi-directional use the arrangement of FIG. 9 is provided with switching means 40′ by which signal connections, the use of which is not necessary for the intended application, i.e. for a write or a read process, can be interrupted. Feeding of the sampling signal 3′ to slave delay-locked loop 300′ and connection of the data memory signal 4 to the synchronisation block 70′ are interrupted during write processes, for example.
FIG. 10 shows a further circuit block constructed on the master-slave principle for a memory interface and used for generating and synchronising control clock and command and addressing signals. The clock signal 1 is fed to a slave delay-locked loop 400′ constructed similarly to slave delay-locked loop 300′ of FIG. 9. Output clock signals 7, 8 of the circuit block are again generated via a multiplexer 420′, to which differently delayed clock signals tapped at the individual delay elements 115′ of the delaying means 110′ of the slave delay-locked loop 400′ are fed. The multiplexer 420′ is driven corresponding to the arrangement in FIG. 9 by a control signal generated by a list stored in a memory 450′ and a control register 430′. By means of this circuit block addressing and command signals 11, 12, 13 are conducted to the memory as addressing and command signals 11′, 12′, 13′ synchronised with the clock signal 1 via flip-flop elements 460 driven by the clock signal 1. The output clock signals 7, 8 of slave delay-locked loop 400′ act as control clock signals for the memory. The task of slave delay-locked loop 400′ is in this case to guarantee that the control clock signals 7, 8 are synchronised with the addressing and command signals 11′, 12′, 13′ at the location of the memory. A defined phase relationship to the sampling signal 3′ and the memory data signal 4 is further necessary. In order to be able to guarantee the required signal strengths at the location of the memory the output signals of the circuit block illustrated in FIG. 10 are output via buffers or line drivers 45′.
The previously described use of the master slave principle for generating and synchronising clock, sampling and data signals and also command and addressing signals guarantees independent selection of the phase relationship for the individual output clock signals 3a, 3b, 3c, 7, 8. A problem with this known solution for setting the delay of clock signals is, however, that the desired phase relationship is preset purely statically, preferably based on an expected value for differences in delay of the individual signals. In this way problems arise in particular if the pulse-duty ratio of the clock signal 1 is subject to fluctuations. Only deviations of the phase relationships which are considerably smaller than the length of a symbol, i.e. typically of a period length of the clock signal 1 may occur. However, this requirement cannot necessarily be guaranteed, in particular for high-frequency memory media. If there are greater fluctuations of the phase shift this leads to a loss of data which can be compensated for only by complex clock and data recovery mechanisms.
A general problem in delay-locked loops is that they react sensitively to errors in the pulse-duty ratio, a so-called duty cycle distortion, which may occur both in the input-side clock signal and within the delaying means. It is further necessary that a clock signal with a high spectral purity and low noise is used as input signal.
Both analog and digital signals can be used as control signals for the delaying means. In the case of analog control signals, however, there is the problem of great sensitivity with respect to interference towards scattering in by internal or external interferers. In this case there are resulting undesired deviations or additional noise within the delaying means. Neither can these problems be avoided by embodying the control loop in differential switching technology. Especially problematical is the use of analog control signals in an arrangement constructed on the above-described master-slave principle. In this case in some circumstances the control signal has to be transmitted to the slave delay loop over a greater distance. This gives rise to increased susceptibility to interference and noise.